The speed of memory devices has increased with the reduction in operating voltages and in the characteristic feature dimensions found in semiconductor devices. However, conventional memory devices are highly susceptible to soft errors.
Soft errors can be caused by, for example, the impact of cosmic rays, or other radiation. In memory devices, these soft errors can occasionally change a data bit in a stored word of data. One method long practiced for enhancing the reliability of stored data bits is a parity check. The simple parity check relies on a parity bit, a memory cell separate from those used in storing the data word. The parity bit is set to logical “1” or “0” in order to make the total count of set bits in a stored word of memory either an even number or an odd number. While being able to very quickly and inexpensively find a single-bit error in a word, simple parity cannot detect an error in two bits, or four, since the total count parity remains the same. Simple parity checking is also unable to repair a bit in error since it cannot detect which bit in a word is in wrongly set.
In error correcting code (ECC) applications, a specific set of bits are calculated for each memory location as it is written. This requires more parity cells to be associated with each memory location, but multi-bit errors can be detected and cured. However, in using ECC, the required increase in memory cells can cause an increase cost of manufacture.
One common method of parity checking is that of scanning through a memory array, during memory idle cycles, to scan for parity errors. In this method, one memory word at time is scanned. While this method ensures thorough memory scanning, it sometimes requires that other operations be held up in order to complete the scan. This can result in delays in the memory operation and a dedicated read port is sometimes needed to access one word each clock cycle.
Accordingly, there is a need for a method for scanning parity check bits that does not delay memory read/write operations that can be implemented with a minimal impact on memory chip real estate usage and that ensure a complete memory scan.